MC68360EM25L
MC68360 QUad Integrated Communication Controller (QUICC)
QUICC Key Features
The following list summarizes the key MC68360 QUICC features:
CPU32+ Processor (4.5 MIPS at 25 MHz)
32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
Background Debug Mode
Byte-Misaligned Addressing
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0–25-MHz Operation)
Slave Mode To Disable CPU32+ (Allows Use with External Processors)
Multiple QUICCs Can Share One System Bus (One Master)
MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
Memory (SRAM), Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
Four CAS lines, Four WE lines, One OE line
Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory)
Special Features for MC68040 Including Burst Mode Support
Four General-Purpose Timers
Superset of MC68302 Timers
Four 16-Bit Timers or Two 32-Bit Timers
Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
Single Address Mode for Fastest Transfers
Buffer Chaining and Auto Buffer Modes
Automatically Performs Efficient Packing
32-Bit Internal and External Transfers
System Integration Module (SIM60)
Bus Monitor
Double Bus Fault Monitor
Spurious Interrupt Monitor
Software Watchdog
Periodic Interrupt Timer
Low Power Stop Mode
Clock Synthesizer
Breakpoint Logic Provides On-Chip Hardware Breakpoints
External Masters May Use On-Chip Features Such As Chip Selects
On-Chip Bus Arbitration with No Overhead for Internal Masters
IEEE 1149.1 Test Access Port
Interrupts
Seven External IRQ Lines
12 Port Pins with Interrupt Capability
16 Internal Interrupt Sources
Programmable Priority Between SCCs
Programmable Highest Priority Request
Communications Processor Module (CPM)
RISC Controller
Many New Commands (e.g., Graceful Stop Transmit, Close RxBD)
224 Buffer Descriptors
Supports Continuous Mode Transmission and Reception on All Serial Channels
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