ISPLSI1048C-50LG
In-System Programmable High Density PLD
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
8000 PLD Gates
96 I/O Pins, 12 Dedicated Inputs, 2 Global Output
Enables
288 Registers
High-Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
Small Logic Block Size for Random Logic
Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E2
CMOS®
TECHNOLOGY
fmax = 50 MHz Maximum Operating Frequency
tpd = 22 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile E2
CMOSTechnology
100% Tested at Time of Manufacture
IN-SYSTEM PROGRAMMABLE
In-System Programmable™ (ISP™) 5-Volt Only
Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
Reprogram Soldered Devices for Faster Debugging
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
Complete Programmable Device Can Combine Glue
Logic and Structured Designs
Four Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
Superior Quality of Results
Tightly Integrated with Leading CAE Vendor Tools
Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
PC and UNIX Platforms
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