ISPLSI2032VE110LJ44
3.3V In-System Programmable High Density SuperFAST™ PLD
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
1000 PLD Gates
32 I/O Pins, Two Dedicated Inputs
32 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
Small Logic Block Size for Random Logic
100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V Devices
3.3V LOW VOLTAGE 2032 ARCHITECTURE
Interfaces With Standard 5V TTL Devices
HIGH PERFORMANCE E2
CMOS®
TECHNOLOGY
fmax = 300 MHz Maximum Operating Frequency
tpd = 3.0 ns Propagation Delay
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
3.3V In-System Programmability Using Boundary
Scan Test Access Port (TAP)
Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
Reprogram Soldered Devices for Faster Prototyping
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
Lead-Free Package Options
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