74LVC4245AD

 

 

FEATURES

 In accordance with JEDEC

standard no. 8-1A

 Wide supply voltage range:

3 V port: 1.5 to 3.6 V

5 V port: 1.5 to 5.5 V

 CMOS low power consumption

 Direct interface with TTL levels

 Control inputs accept voltages up to 5.5 V.

 

DESCRIPTION

The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate

CMOS device, superior to most advanced CMOS compatible TTL families.

The 74LVC4245A is an octal dual supply translating transceiver featuring

non-inverting 3-state bus compatible outputs in both send and receive

directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V

supply environment.

The 74LVC4245A features an output enable (OE) input for easy cascading and

a send/receive (DIR) input for direction control. (OE) controls the outputs so

that the buses are effectively isolated.

In suspend mode, when VCCA is zero, there will be no current flow from one

supply to the other supply. The A-outputs must be set 3-state and the voltage

on the A-bus must be smaller than Vdiode (typ. 0.7 V). VCCA ≥ VCCB (except in

suspend mode).

 

 

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