EP2S90F1020C4

 

 

The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper 

SRAM process and features a new logic structure that maximizes 

performance, and enables device densities approaching 180,000 

equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of 

on-chip, TriMatrix™ memory for demanding, memory intensive 

applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) 

multipliers for efficient implementation of high performance filters and 

other DSP functions. Various high-speed external memory interfaces are 

supported, including double data rate (DDR) SDRAM and DDR2 

SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data 

rate (SDR) SDRAM. Stratix II devices support various I/O standards 

along with support for 1-gigabit per second (Gbps) source synchronous 

signaling with DPA circuitry. Stratix II devices offer a complete clock 

management solution with internal clock frequency of up to 550 MHz 

and up to 12 phase-locked loops (PLLs). Stratix II devices are also the 

industry’s first FPGAs with the ability to decrypt a configuration 

bitstream using the Advanced Encryption Standard (AES) algorithm to 

protect designs.

 

 

 

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