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PDI1394P23BD

PDI1394P23BD
型号:PDI1394P23BD
品牌:PHI PHI
批号:13+RoHs
封装:QFP
原价:10.5
数量:550250
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详细描述

 PDI1394P23BD

2-port/1-port 400 Mbps physical layer interface
 
 
FEATURES
 Fully supports provisions of IEEE 1394–1995 Standard for high
performance serial bus and the P1394a–2000 Standard.
1
 Fully interoperable with Firewire and i.LINK implementations of
the IEEE 1394 Standard.
2
 Full P1394a support includes:
 Connection debounce
 Arbitrated short reset
 Multispeed concatenation
 Arbitration acceleration
 Fly-by concatenation
 Port disable/suspend/resume
 Provides two 1394a fully-compliant cable ports at
100/200/400 Mbps.
 Fully compliant with Open HCI requirements
 Interface to link-layer controller supports both low-cost bus-holder
isolation and optional Annex J electrical isolation
 Supports extended bias-handshake time for enhanced
interoperability with camcorders
 Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
 Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
 Cable ports monitor line conditions for active connection to remote
node.
 Separate cable bias (TPBIAS) for each port
 Logic performs system initialization and arbitration functions
 Encode and decode functions included for data-strobe bit level
encoding
 Incoming data resynchronized to local clock
 Single 3.3 volt supply operation
 Minimum VDD of 2.7 V for end-of-wire power-consuming devices
 Interoperable with link-layer controllers using 3.3 V and 5 V
supplies
 Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
 Node power class information signaling for system power
management
 Cable power presence monitoring
 Power down features to conserve energy in battery-powered
applications include:
 Automatic device power down during suspend
 Device power down terminal
 Link interface disable via LPS
 Inactive ports powered-down
 While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
 Can be used as a one port PHY without the use of any extra
external components
 Low-cost 24.576 MHz crystal provides transmit, receive data at
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
 Does not require external filter capacitors for PLL
 LQFP package is function and pin compatible with the Texas
Instruments TSB41LV02AE and TSB41AB2E 400 Mbps
PHYs.
 
 
Because of wholesale price is different from sample price, our website ca not state   Please send your required part number via emai to Sales@hkmjd com or add our skype id mjdccm898 for online talking  As we as welcome you ca us : 0755-83957301  We wi send offer for you;  Sometimes manufacturer's price is unstable, so we don't adjust price i time  if you fee price is a little high for you, just fee free to contact us for consultatio  Thank you for your support !
 
 
 
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