S3F9454BZZ-DK94

 

 

 

FLAG DESCRIPTIONS

33Overflow Flag (FLAGS.4, V)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128.

It is also cleared to "0" following logic operations.

 

Sign Flag (FLAGS.5, S)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A

logic zero indicates a positive number and a logic one indicates a negative number.

 

Zero Flag (FLAGS.6, Z)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that

test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

 

Carry Flag (FLAGS.7, C)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7

position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.

Program instructions can set, clear, or complement the carry flag.

 

 

 

 

 

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